1. Field of the Invention
The present invention relates to a double-RESURF-type lateral diffused MOSFET (LDMOS) transistor having separately patterned N-type and P-type buried layers, and particularly to a method for fabricating such double-RESURF LDMOS transistors using a single “shared” mask.
2. Related Art
RESURF (Reduced Surface Field) technology is one of the most widely used methods in Power management applications for providing high voltage (HV) transistors exhibiting both a high break down voltage (BV) and a low specific resistance (RDSON). The RESURF technique is achieved by placing a PN junction below the extended drain in a LDMOS transistor such that a depletion layer extending from the PN junction reaches the device surface, and as a result the BV of the device is increased significantly. The RESURF technique involves forming laterally diffused metal oxide semiconductor (LDMOS) transistors in a relatively thin layer of epitaxial layer, which is less time consuming to produce, and the resulting “RESURF LDMOS” transistors having a much higher BV and lower RDSON than conventional vertical power transistors.
FIG. 7 is a cross sectional view of a conventional double-RESURF LDMOS transistor 30. The phrase “double RESURF” refers to a technique used to enhance the BV of an LDMOS transistor while maintaining a low RDSON, or in other words to increase the BV-to-RDSON ratio. The double RESURF technique involves depleting the extended drain area in an LDMOS from two sides, for example, from the bottom and from the top in y direction, forming a drift layer (N-DRIFT) below the gate oxide. In practice, as indicated in FIG. 7, the depletion of the drift layer from two directions is achieved by forming a lower PN junction (referred to as “PN junction below”) below the deep N-well that serves to deplete the drift layer region from the bottom, and placing a polycrystalline silicon gate (referred to as “drift poly”) on top of the oxide that forms part of the drift layer (extended drain area) and serves to deplete the extended drain from the top. The direction of the depletion layers extending from the top and bottom are indicated by the dashed-line arrows marked “TOP” and “BOTTOM” in FIG. 7, respectively. Although these depletions are applied from vertical “sides” (i.e., top and bottom), these depletions result in a horizontal electrical field. The key point of depleting the drift region from two sides is the shape of this horizontal electrical field. Specifically, by depleting the drift region from two sides, a double RESURF LDMOS has a constant electrical field with a rectangular shape, in comparison to the electric field generated in single RESURF LDMOS, which has a linear triangular shape. The rectangular shape of the horizontal field gives double RESURF LDMOS transistors a much higher BV compared to comparable single RESURF LDMOS transistors having the triangular shaped electrical field generated by single RESURF. Double RESURF therefore provides much higher BV for a given geometry and doping level (i.e., for a given BV, a transistor formed using double RESURF technology has much smaller geometry (footprint) than a transistor formed by single RESURF technology). In other words, double RESURF technology allows much lower RDSON (e.g., as low as 50%-60%) in comparison to single RESURF technology.
An issue associated with the use of RESURF LDMOS transistors in high current applications involving inductive loads is that unwanted current injection to the substrate is generated by way of a parasitic bipolar transistor formed by the body/deep-N-well/substrate regions of the RESURF LDMOS transistor. To avoid the excess minority injection causing this parasitic bipolar, a common practice is to use an N+ buried layer (NBL) formed under the entire deep-N-well region in which the LDMOS transistor is formed (i.e., in the region where the the epitaxial layer meets the base underlying substrate). Although such LDMOS transistors with NBL are superior to earlier LDMOS transistors in high current applications, the NBL acts to reduce the BV, and also results in higher RDSON for a given breakdown voltage.
Conventional double-RESURF LDMOS transistor 30 (FIG. 7) also illustrates a recent methodology that takes advantage of the NBL isolation while maintaining high BV is to form a P+ buried layer (P-Well) in the epitaxial layer between the NBL and the deep N-well located below the LOCOS gate oxide and containing the drain portion of the LDMOS. The P-Well serves to gain back the desired high BV for devices having smaller geometries by inducing depletion in the drift region of the epitaxial layer, and is formed by implanting ions of an P-type material (e.g., Boron (B)) in the semiconductor substrate of the device over a portion of the NBL, and then updiffusing the P-type ions into an epitaxial layer to provide the desired position of the P-well between the NBL and a N-well containing the drain portion of the LDMOS. A problem with this approach is that it requires the use of a complicated boron implant process that utilizes extra high energy from the top of the device to be buried below the deep N-well, as disclosed in “A Double RESURF LDMOS With Drain Profile Engineering for Improved ESD Robustness” by V Parthasarathy Et Al, in IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 4, APRIL 2002 p 212. The Boron, which forms the PBL, is implanted with the Antimony (Sb) that forms the NBL, and diffuses faster than the Sb, and so desirably forms the PBL between the deep N-well and the NBL. However, the process requires the formation of two separate masks having specific thicknesses in order to effectively implant the Boron and Sb at the proper dosages and depths such that they form the required PBL and NBL regions.
Another problem associated with the conventional approach of implanting a PBL from the top is that it is very difficult to scale the implant process for higher voltages. That is, in the prior art case to scale the voltage deeper more energetic implant is needed and is also limited. Yet another problem associated with the conventional approach is that patterning the P-well below the N-well (extended drain implant) is either restricted to the layout of the extended drain or requires an extra mask. That is, it is important to be able to pattern the PBL (independently from the NBL) in order to optimize the BV Vs. RDSON characteristics of the cell due to interactions between the drift layer and the source side and drain side affecting the resulting BV and RDSON, and requiring this degree of freedom for simultaneous optimization of BV and RDSON.
What is needed is a method for producing an improved double-RESURF LDMOS transistor having a P-type buried layer that addresses the problems set forth above. What is particularly needed is a cost effective and reliable method for generating double-RESURF LDMOS transistors having separately patterned N-type and P-type buried layers, with the NBL optimized for isolation purposes (i.e., to “kill” the parasitic bipolar) and the PBL optimized for improving the BV and RDSON, that can be incorporated into a standard process flow with minimal modifications.